/*
 * file: tran.v
 * test for tran gates
 */

module cucu;

  reg r1, r2;
  wire w1, w2;

  tran t (w1, w2);

  wire [1:0] aw1, aw2;
  reg [1:0] ar1, ar2;

  tran at [1:0] (aw1, aw2);

  assign w1 = r1, w2 = r2;
  assign aw1 = ar1, aw2 = ar2;

  task do_tran;
  begin
    $display("single tran gate:");
    $display("r1\tw1\t\t\tw2\t\t\tr2");
    $display("---------------------------------------------------------");
    r1 = 0;
    r2 = 0;
    r2 <= 'bx; //here we force the wirez to update themselves.
               //i'm not sure if the behaviour in the initial state is
	       //ok like this...
    $strobe("%b\t%v\t%v\t%b", r1, w1, w2, r2);
    #1;
    r2 = 0;
    $strobe("%b\t%v\t%v\t%b ", r1, w1, w2, r2);
    #1;
    r1 = 'b1;
    $strobe("%b\t%v\t%v\t%b", r1, w1, w2, r2);
    #1;
  end
  endtask

  task do_tran_a;
  begin
    $display("\n\na tran array:");
    $display("ar1\taw1\t\t\taw2\t\t\tar2");
    $display("---------------------------------------------------------");
    ar1 = 0;
    $strobe("%b\t%v\t%v\t%b", ar1, aw1, aw2, ar2);
    #1;
    ar2 = 0;
    $strobe("%b\t%v\t%v\t%b", ar1, aw1, aw2, ar2);
    #1;
    ar1 = 'b11;
    $strobe("%b\t%v\t%v\t%b", ar1, aw1, aw2, ar2);
    #1; 
  end
  endtask

  initial begin
    do_tran();
    do_tran_a();
  end
endmodule












